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STV2000
I2C SINGLE FREQUENCY DEFLECTION PROCESSOR AND 70 MHz RGB PREAMPLIFIER
PRELIMINARY DATA
FEATURES
Horizontal deflection s Single frequency, self adaptive oscillator. s TTL compatible positive going sync. 2 s IC controlled: H-position, Pin Cushion, Keystone, Parallelogram, Side Pin Balance,Hamplitude. s DC East/West feedback. s DC controls: H-width breathing compensation. s X-Ray protection Vertical deflection s Vertical ramp generator. s Wide range AGC loop. s TTL compatible positive going sync, no extra pulses. 2 s I C controls: vertical position and S-correction. s DC controls: height breathing compensation. Video preamplifier s 3-channel 70MHz bandwidth RGB preamplifier. s 5ns typical rise and fall time at 4VPP. 2 s I C controls: RGB contrast, cut-off, brightness, contrast up-date during vertical retrace time. s ABL will reduce gain (contrast). s 0.514V typical video input signal for normal display. I2C Main features 2 s I C interface (slave) 100kHz max. 2 s All I C controlled DAC are 7bit, except for RGB gain and cut-off. s Power- on- reset at 5 V (VDD). s 0.5 to 4 V static DAC output. Supply voltage & power s 5 V/10.5 V dual supply. s Max power consumption: 1.2W
DESCRIPTION
The STV2000 is an I2C-controlled monolithic integrated circuit assembled in a TQFP44 plastic package. It combines both a deflection block (horizontal and vertical, single frequency with very powerful geometry correction) and a 70MHz RGB pre-amplifier.
TQFP44 ORDER CODE :
PIN CONNECTIONS
FILTER PLL2C HGND Hfly Href Hout Ro Co PLL1F Hin FC1
Vin Vref VAGCAP VGND VCAP Vout VBRTHin VRB VAVcc Out1 Cut-off 1
44 43 42 41 40 39 38 37 36 35 34 33 1 32 2 31 3 30 4 29 5 28 6 27 7 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 AGND Out2 Cut-off2 PGDN Out3 Cut-off3 PVcc In1 ABLin In2 DAC
LGDN SAVcc SCL SDA V DD (5V) EWout EWFBin HBRTHin
N.C. VBDC
In3
Version 3.0
April 2000
This is preliminary information on a new product now in development. Details are subject toDetails are subject to change without notice. in development or undergoing evaluation. change without notice.
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TABLE OF CONTENTS
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SYNC INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 I2C READ/WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 HORIZONTAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VERTICAL SECTION) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VIDEO PRE-AMP SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LOGIC SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C BUS ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TYPICAL OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 OPERATING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SCANNING PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PRE-AMPLIFIER PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STAND-BY MODE AND PROTECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 INTERNAL SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2
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STV2000
PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name Vin Vref VAGCCAP VGND VCAP Vout VBRTHin VRB VAVcc OUT1 Cut-off1 AGND OUT2 Cutoff2 PGND OUT3 Cutoff3 PVcc IN1 ABLin IN2 DAC IN3 VBDC N.C. HBRTHin EWFBin EWout VDD SDA SCL SAVcc LGND Hout Href Hfly HGND PLL2C Filter PLL1F Co Ro FC1 Hin Function Vertical Sync Input Vertical Section Reference Voltage Vertical AGC Loop Capacitor Vertical Section Ground Vertical Sawtooth Generator Capacitor Vertical Output Vertical Breathing DC Input Vertical Ramp Filter Video Section Analog Supply (10.5V typ) Video Output 1 Cut-off1 DAC voltage output pin Video Analog Ground Video Output 2 Cut-off2 DAC voltage output pin Video Section Power Ground Video Output 3 Cut-off3 DAC voltage output pin Video Section Power Supply (10.5V typ) Video Input 1 Video Automatic Beam Current Compensation Input Video Input 2 7bits DAC Voltage Output Video Input 3 Vertical Blanking Output with DC level adjusted by DAC Not to be connected Horizontal Breathing Compensation DC Input EW Correction Feedback Input EW Buffer Output Bus, Scanning Logic and Video Logic Supply (5V typ) I2C Data Input I2C Clock Input Scanning Section Analog Supply (10.5Vtyp) Bus and Scanning Power Ground Horizontal Driver Output, open collector Horizontal Section Reference Voltage Horizontal Flyback Input, Positive Horizontal Section Ground PLL2 Loop Filter Horizontal Filter Capacitor (HPOS) PLL1 Loop Filter Horizontal Oscillator Capacitor Horizontal Oscillator Resistor PLL1 filter capacitor Horizontal Sync Input
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3
4/38 PLL1F 40 SAVCC 32 Href 35 Vref 2 Vpos Vamp Scorr VOSC RAMP Generator SPB X2 Geometry Tracking X2 EWPCC EW OUTPUT 28 EWout 27 EWFBin Href Vref Phase Freq Comp VCO Phase Comp Phase Shifter HOUT Buffer Safety Filter 39 FC1 Ro 43 42 Co HFly 41 36 PLL2C 38 Hout 34 Hin 44 Vin 1 HGND 37 VGND 4 VCAP 5 VAGCCAP 3 VBRTHin 7 VRB Vout 6 8 I2C BUS DECODER Hsync Clamp Contrast LATCHES & DACs Brightness Drive BPCP Output Stage DAC KeyBal X HFly Hsync Vsync KEYST
BLOCK DIAGRAM
26 HBRTHin 20 ABLin
STV2000
+
H Breathing ABL
Blanking
24 VBDC 22 DAC 9 VAVCC 12 AGND 10 OUT 1 11 Cut-off 1 18 PV CC 13 OUT 2 14 Cut-off 2 15 PGND 16 OUT 3
SDA 30 SCL 31 VDD 29 LGND 33 IN1 19
IN2 21
IN3 23
17 Cut-off 3
STV2000
STV2000
ABSOLUTE MAXIMUM RATINGS
Symbol SAVcc VAVcc PVcc Vdd VESD Tstg Tj Toper Parameter Scanning Section Analog Supply Voltage Video Section Analog Supply Voltage Supply Voltage for Video Pre-Amp Section Logic Section Supply Voltage ESD susceptibility HBM model 100pF & 1.5k EIAJ Norm 200pF & 0 Storage Temperature Junction Temperature Operating Temperature (Device ambient) Value 13.5 13.5 13.5 5.5 2 300 -40 to 150 150 0 to 70 Unit V V V V kV V
oC o o
C C
THERMAL DATA
Symbol R TH(j-a) Parameter Junction to Ambient Thermal Resistance (MAX) Value 46 Unit
oC/W
SYNC INPUT
Operating Conditions (VDD = 5V, Tamb = 25C)
Symbol HSVR MinD Mduty VSVR VSW VSD Parameter Voltage on Hin Min Hin pulse duration Max Hin Duty Cycle Voltage on Vin Min Vin pulse duration Max Vin Duty Cycle Test Conditi ons Pin 44 Pin 44 Pin 44 Pin 1 Pin 1 Pin 1 0 5 15 Min 0 0.7 25 5 Typ Max 5 Unit V us % V us %
Electrical Characteristics (VDD = 5V, Tamb = 25C)
V INTH RIN Horizontal & Vertical Input Logic Level Horizontal & Vertical Pull-Up Resistor Low Level High Level 0.8 2.2 200 V V k
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STV2000
I2C READ/WRITE
Electrical Characteristics (VDD = 5V, Tamb = 25C)
Symbol FSCL TLOW THIGH VINL VINH VACK Parameter Maximum Clock Frequency Low Period of the SCL Clock High Period of SCL Clock SDA & SCL Input Low Level Voltage SDA & SCL Input High Level Voltage Acknowledge Output Voltage on SDA input with 3mA 3 0.4 1.3 0.6 1.5 Test Conditi ons Min Typ Max 100 Unit kHz us us V V V
HORIZONTAL SECTION
Operating Conditions
Symbol VCO Ro(min) Co(min) Fmax Minimum Oscillator Resistor Minimum Oscillator Capacitor Maximum Oscillator Frequency 6 390 150 k pF kHz Parameter Test Conditi ons Min Typ Max Unit
OUTPUT SECTION IHFB IHOUT Horizontal FlyBack Input Maximum Current Horizontal Drive Output Maximum Sink Current 5 15 mA mA
Electrical Characteristics (VDD = 5V, Tamb = 25C)
Symbol Parameter Test Conditi ons Min Typ Max Unit SUPPLY AND REFERENCE VOLTAGES Vcc Vdd Icc Idd VHREF VVREF IHREF IVREF Supply Voltage Supply Voltage Supply Current Supply Current Horizontal Reference Voltage Vertical Reference Voltage Horizontal Reference Maximum Source Current Vertical Reference Maximum Source Current I=-2mA I=-2mA 7.4 7.4 9.5 4.5 10.5 5 30 5 8 8 8.6 8.6 5 5 11.5 5.5 V V mA mA V V mA mA
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STV2000
Operating Conditions
Symbol 1st PLL SECTION V clamp VVCO AVCO HPHASE VPMIN VPTYP VPMAX IPLL1-UL I PLL1-L fO dfo/dT VCO clamp Voltage range VCO clamp Voltage, at POR VCO Gain Horizontal Phase Adjustment Range Horizontal Phase Minimum Typical Maximum PLL1 Charge Pump Current Free Running Frequency, no input at POR, lower clamp voltage at max. Free Running Frequency Thermal Drift VHREF=8V VHREF=8V Ro=6490, Co=820pF, dF/dV=1/11RoCo % of Horizontal Period SubAdd 07 X1111111 X1000000 X0000000 Unlocked Locked Ro=6490, Co=820pF 3.0 3.8 17.1 +/-10 2.8 3.4 4.0 +/-140 +/-1 65 -150 3.8 V V kHz/V % V V V A mA kHz ppm/ oC Parameter Test Conditi ons Min Typ Max Unit
2nd PLL SECTION & HORIZONT AL OUTPUT SECTION VTHFB JitterH H DC Flyback Input Threshold Voltage Horizontal Jitter Horizontal Drive Output Duty Cycle (Ratio of Power Transistor OFF time to Period) Internal Clamp Level on PLL2 Filter Threshold Voltage to Stop H-Out, V-Out, Reset ABL when VccVphi2 VSCinh VsatHD
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STV2000
VERTICAL SECTION
Symbol Parameter Test Conditi ons Min Typ Max Unit
Electrical Characteristics (VDD = 5V, Tamb = 25C)
VERTICAL RAMP SECTION VRBOT VRTOP VRTOPF TVDIS FFRV ASFR RAFD RLIN Voltage at Ramp Bottom Point Voltage at Ramp Top Point with Sync V VREF=8V V VREF=8V 2 5 VRTOP0.1 70 100 50 200 0.5 165 V V V s Hz Hz ppm/Hz %
Voltage at Ramp Top Point without Sync V VREF=8V Vertical Sawtooth Discharge Time Vertical Free Running Frequency (S correction inhibited) Auto-Sync Frequency Range Ramp Amplitude Drift Versus Frequency at Maximum Vertical Amplitude Ramp Linearity at Vcap pin with S Correction inhibited Vertical Position Adjustment Voltage with VOUT mean value COSC=150nF C OSC=150nF COSC=150nF C OSC=150nF 50Hz 165Hz 2.5V < VOSC < 4.5V Sub-Add=09 X0000000 X1000000 X1111111 Sub-Add=08 10000000 11000000 11111111
VPOS
3.65
3.2 3.5 3.8 2.25 3 3.75 +/-5 2
3.3
V V V V V V mA V % %
VOR
Vertical Output Peak to Peak Voltage
2.5
3.5
IVOUT V VRB
Vertical Output Maximum Current Vertical Ramp Filter Voltage Max Vertical S-Correction Amplitude S-Correction inhibited, DV/Vpp at TV/4 S-correction Maximum, DV/Vpp at 3TV/4 Sub-Add 0A 0XXXXXXX 11111111
dVS
-4 +4
EAST/WEST FUNCTION (output is internal, can be checked at EWFB pin indirectly) DC Output Voltage with Typical VPOS and Keystone inhibited With external driver connected as unity gain buffer DC Output Voltage Thermal Drift (Non-test Parameter) Parabola Amplitude with Max VAMP, Typ VPOS, Keystone inhibited Sub-add 0C 11111111 11000000 10000000
EWDC
2.0
V
TDEWDC
100
ppm/ oC
EWPARA
1.0 0.5 0
V V V
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STV2000
Symbol
Parameter Parabola Amplitude Function of VAMP Control (tracking between VAMP & EW) with Typ VPOS, Keystone, Typ EW Amplitude. Keystone Adjustment Capability with Typ VPOS, EW inhibited and Max Vertical Amplitude Intrinsic Keystone Function of VPOS Control (tracking between VPOS and EW) with Max EW Amplitude and Max Vertical Amplitude A/B Ratio B/A Ratio
Test Conditi ons Sub-address 08 10000000 11000000 11111111 Sub-address 0B 10000000 11111111 Sub-add 09
Min
Typ
Max
Unit V V V
EWtrack
KeyAdj
0.2 0.2
Vpp Vpp
KeyTrack
X0000000 X1111111
0.52 0.52
INTERNAL DYNAMIC HORIZONTAL PHASE CONTROL SBPpara Side Pin Balance Parabola Amplitude with Max VAMP, Typ VPOS and Parallelogram inhibited Side Pin Balance Parabola Amplitude function of VAMP Control (tracking between VAMP & SPB) with Max SPB, Typ VPOS and Parallelogram inhibited Parallelogram Adjustment Capability with Max VAMP, Typ VPOS and Max SPB Intrinsic Parallelogram Function of VPOS Control (tracking between VPOS and DHPC) with Max VAMP, Max SPB and Parallelogram inhibited A/B Ratio B/A Ratio VERTICAL BREATHING COMPENSATION VBRrng VBRadj Input DC Breathing Control Range Vertical Output Variation versus DC Breathing Control Vbrin>V VREF Vbrin=4V 1 0 -10 10.5 V % % Sub-add 0E 11111111 10000000 Sub-add 08 10000000 11000000 11111111 Sub-add 0F 11111111 10000000 Sub-add 09 +1.4 -1.4 %TH %TH %TH %TH %TH %TH %TH
SPBtrack
0.5 0.9 1.4
ParAdj
+1.4 -1.4
Partrack
X0000000 X1111111
0.52 0.52
HORIZONTAL SIZE CONTROL Hsize Hsize output DC voltage sitting on top of EWDC=2.0V sub-add 0D X0000000 X1111111 0 2.4 V V
EW OUTPUT BUFFER Iewout EWFB EWout pin max source current EWoutput referred DC voltage 3.0 2.0 mA V
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STV2000
Symbol
Parameter
Test Conditi ons
Min
Typ
Max
Unit
HORIZONTAL BREATHING COMPENSATION HBRdc HSC Breathing input DC Control Range Horizontal size compensation, EW DC voltage variation under full range of HBRdc 1 0.4 10.5 V V
VIDEO PRE-AMP SECTION
Symbol Parameter Test Conditi ons Min Typ Max Unit
DC Electrical Characteristics (VAVCC = PVCC = 10.5V, Tamb =
VAV cc PVcc IS VIN VOUT V DC Video Section Analog Supply Voltage Power Section Supply Voltage Supply Current of VAVcc & PVcc Video Input Voltage Amplitude Typical Output Voltage Range Output DC level (Black level)
25oC)
9.5 9.5 10.5 10.5 60 0.7 0.5 1.5 1 7 11.5 11.5 V V mA Vpp V V
AC Electrical Characteristics (VAVCC = PV CC = 10.5V, CL = 12pF, RL = 1K, Tamb =
Symbol AV Parameter Maximum Gain Condition Max Contrast and Drive I2C Gainwin = 1 VIN = 0.7Vpp Contrast and Drive at POR Min Typ 18
25oC)
Max Unit dB
CAR DAR GM
Contrast Attenuation Range Drive Attenuation Range Gain Match
30 30
dB dB dB
VIN = 0.7Vpp, VOUT = 4Vpp, Contrast and Drive= 0.87Max VIN=0.7Vpp, VOUT = 4Vpp, Contrast and Drive = 0.87Max At -3dB f=1MHz, VIN=1Vpp, VOUT = 1Vpp VIN = 0.7Vpp, VOUT =4Vpp,Contrast and Drive=0.87Max CLOAD=5pF
+-0.1
BW
Large Signal Bandwidth
70
MHz
DIS
Video Output Distortion
0.3
%
tR, tF
Video Output Rise and Fall Time
5
ns
dVo BRT RL Tsample
Overshoot of output with respect to actual output amplitude Brightness max DC level Brightness min DC level Equivalent Load on Video Output Hold time
5 2.5 0
7
% V V k ms
Tj1
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STV2000
Symbol Thold CT Sample time
Parameter
Test Conditi ons
Min 1
Typ
Max
Unit s
Crosstalk Between Video Channels
VIN = 0.7Vpp, VOUT = 2.5Vpp, Contrast and Drive=0.7Max f=1MHz
44
dB
CUTOFF VCUTOFF CUTOFF DAC output voltage Output sink current Output source current 00000000 10000000 11111111 2 0.5 2.5 4.5 100 V V V A mA
ICUTOFF
ABL COMPENSATION R ABL GABL THABL DAC sub-add 12 00000000 01000000 01111111 1.5 0.5 2.25 4.0 2 V V V mA ABL Input resistor ABL minimum Attenuation ABL maximum Attenuation ABL latch function activation threshold (High beam current detection) VABL=5.3V VABL=2.8V 0 10 0 12 1 k dB dB V
VDAC
ILOAD=100uA
IDAC
Source current
LOGIC SECTION
DC Electrical Characteristics (VAVCC = PVCC = 10.5V, Tamb = 25oC)
Symbol Parameter Condition Min Typ Max Unit V BLANKING OUTPUT SECTION Blanking output high voltage VBDC Blanking output low voltage I2C adjustable Output sink current Vertical blanking time (gated with Hflyback) 22 sub-add10 1X000000 1X111111 7 1 4.5 0.3 V V V mA H cycle
IBLK TBLK
SUPPLY VOLTAGE THRESHOLD VTHPD1 VTHPD2 Supply first threshold voltage Supply second threshold voltage 8.5 6.9 V V
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STV2000
I2C BUS ADDRESS TABLE
[0] denotes POR value, X denotes unused data bit and must be set to 0.
D8 D7 D6 WRITE MODE (SLAVE ADDRESS= 8C) Video: 1, on 00 [0], off [1] [0] 01 02 03 04 05 06 07 [1] [1] [1] [0] [0] [0] Hout 0, off [1], on Vramp 0, off [1], on Xray 1, reset [0] S Select 1, on [0], off EW Key 0, off [1], on EW Select 0, off [1], on x SPB Sel 0, off [1], on Parallelog 0, off [1], on VBDC 1, on [0], off POR [0], off 1, reset [0] [0] [0] [0] [0] [0] [1] [1] [1] [1] [0] [0] [0] [0] D5 D4 Contrast [1] Drive 1 [1] Drive 2 [1] Drive 3 [1] [0] [1] Cut off 1 [0] [1] [0] Cut off 2 [0] [1] [0] Cut off 3 [0] [1] [0] Horizontal Phase Adjustment [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [1] [0] [0] [0] [1] [0] [0] D3 D2 D1
[1]
[0]
[1]
[0]
Vertical Ramp Amplitude Adjustment [1] [0] [0] [0] [0] [0] [0]
08
Vertical Position Adjustment [1] [0] [0] [0] S Correction [1] [0] [0] [0] Keystone [1] [0] [0] [0] EW Amplitude [1] [1] [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]
09
0A
0B
0C 0D 0E
Horizontal Amplitude [0] [0] Side Pin Balance [0] Parallelogram [0]
0F
[1] Gainwin [0], 1X 1, 1.5X Powsav 1, on [0], off [1]
[0]
[0]
[0]
[0]
[0]
[0]
Vertical Blanking DC level [1] [1] [1] Brightness [1] [0] x [0] [0] x [1] DAC [0] [0] [1] [0] [1] [0] [0] [1] [1] [1]
10
11 12 13
x
x
[0] [0] PLL1 filter voltage clamp (FVC) [0] [0]
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STV2000
D8 Hlock 0, lock [1], unlock
D7
D6 D5 D4 READ MODE (SLAVE ADDRESS = 8D) Xray 1, on [0], off
D3
D2
D1
Figure 1. EW Output Referred Voltage
B EWPARA A
EWDC Figure 2. Dynamic Horizontal Phase Control Output
EWPARA A
B
DHPC DC
SPBPARA
Figure 3. Keystone Effect on EW Output (PCC Inhibited)
Keyadj
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STV2000
TYPICAL OUTPUT WAVEFORMS
Function Sub Address Pin Byte Specification Effect on Screen
2.25 V
10000000 Vertical Size
3.75 V
11111111
Vertical Position
x0000000 x1000000 x1111111
V OUTDC = 3.2 V V OUTDC = 3.5 V VOUTDC = 3.8 V
Vertical S Linearity
00000000 Inhibited
11111111
VPP
EW Inhibited 10000000 Keystone 11111111
2.0V
0.2Vpp
2.0V
0.2Vpp
EW Inhibited EW Pin Cushion 10000000 11111111
2.0 V
1.0 V 2.0 V
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STV2000
Function
Sub Address
Pin
Byte
Specification
Effect on Screen
10000000 H Amplitude 11111111
5
V
00000000 H Phase 01111111
5 V
Parallelogram Inhibited Side Pin Ballance Control 10000000 11111111
3.7 V 1.4%
1.4% 3.7 V
SPB Inhibited Parallelogram Control 10000000 11111111
3.7 V 1.4%
3.7 V
1.4%
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Contrast Register (Video IN = 0.5VPP, Drive at maximum, I2C Gainwin=1)
Hex b7 0 0 0 0 0 0 0 0 0 0 b6 0 0 0 0 0 0 0 1 1 1 b5 0 0 0 0 0 0 1 0 0 1 b4 0 0 0 0 0 1 0 0 1 1 b3 0 0 0 0 1 0 0 0 1 1 b2 0 0 0 1 0 0 0 0 0 1 b1 0 0 1 0 0 0 0 0 1 1 b0 0 1 0 0 0 0 0 0 0 1 Vpp 0 0.015 0.031 0.062 0.125 0.25 0.5 2 2.812 4 G(dB) -30 -24 -18 -12 -6 0 12 15 18 X POR
Brightness Register (Drive at maximum)
Hex
b5
0 0 0 0 0 0 1 0 0 1 1
b4
0 0 0 0 0 1 0 0 0 0 1
b3
0 0 0 0 1 0 0 0 0 1 1
b2
0 0 0 1 0 0 0 0 0 1 1
b1
0 0 1 0 0 0 0 0 0 0 1
b0
0 1 0 0 0 0 0 0 0 1 1
Vpp
0 0.010 0.020 0.040 0.08 0.16 0.32 0.64 1.28 1.8 2.56
POR
X
Drive1, Drive2, Drive3 Registers (Video IN = 0.5VPP, Contrast at maximum, I2C Gainwin=1)
Hex 00 01 02 04 08 10 20 40 80 B4 FF b7 0 0 0 0 0 0 0 0 1 1 1 b6 0 0 0 0 0 0 0 1 0 0 1 b5 0 0 0 0 0 0 1 0 0 1 1 b4 0 0 0 0 0 1 0 0 0 1 1 b3 0 0 0 0 1 0 0 0 0 0 1 b2 0 0 0 1 0 0 0 0 0 1 1 b1 0 0 1 0 0 0 0 0 0 0 1 b0 0 1 0 0 0 0 0 0 0 0 1 Vpp 0 0.015 0.031 0.062 0.125 0.25 0.5 1 2 2.812 4 G(dB) -30 -24 -18 -12 -6 0 6 12 15 18 X POR
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STV2000
Cutoff1, Cutoff2, Cutoff3 Output values
Hex 00 01 02 04 08 10 20 40 80 B4 FF b7 0 0 0 0 0 0 0 0 1 1 1 b6 0 0 0 0 0 0 0 1 0 0 1 b5 0 0 0 0 0 0 1 0 0 1 1 b4 0 0 0 0 0 1 0 0 0 1 1 b3 0 0 0 0 1 0 0 0 0 0 1 b2 0 0 0 1 0 0 0 0 0 1 1 b1 0 0 1 0 0 0 0 0 0 0 1 b0 0 1 0 0 0 0 0 0 0 0 1 4.5 0.625 X FB pin 0.5 POR
DAC Output DC voltage
Hex b6 0 0 0 0 0 0 0 1 1 0 1 b5 0 0 0 0 0 0 1 0 0 1 1 b4 0 0 0 0 0 1 0 0 0 1 1 b3 0 0 0 0 1 0 0 0 0 0 1 b2 0 0 0 1 0 0 0 0 0 1 1 b1 0 0 1 0 0 0 0 0 0 0 1 b0 0 1 0 0 0 0 0 0 0 0 1 4.0 2.25 X Output dc 0.5 POR
Vertical Blanking Output DC voltage
Hex b5 0 0 0 0 0 0 1 0 0 1 1 b4 0 0 0 0 0 1 0 0 0 1 1 b3 0 0 0 0 1 0 0 0 0 0 1 b2 0 0 0 1 0 0 0 0 0 1 1 b1 0 0 1 0 0 0 0 0 0 0 1 b0 0 1 0 0 0 0 0 0 0 0 1 4.5 X Output dc 1.0 POR
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STV2000
OPERATING DESCRIPTION A SCANNING PART
1. GENERAL CONSIDERATIONS 1.1 Power Supply Typical power supply voltages are 10.5 V for the Deflection and Preamplifier sections (SAVCC, VAVCC and PVCC) and 5.0 V for the logic section (Vdd). Optimum operation is obtained between 9.5 and 11.5 for VCC, and between 4.5 and 5.5 V for VDD. VCC is monitored during the transient phase when switched either on or off, to avoid erratic operation of the circuit. If VCC is inferior to 6.9 V typ., the circuit outputs are inhibited. Similarly, before VDD reaches 4 V, all the I2C registers are reset to their default value (see I2C Control Table). The circuit is internally supplied by several voltage references (typ. value: 8 V) to ensure a good power supply rejection. Two of these voltage references are externally accessible respectively for the vertical and horizontal parts. They can be used to bias external circuitry if ILOAD is inferior to 5 mA. To minimize the noise and consequently the "jitter" on vertical and horizontal output signals, the reference voltages must be filtered by external capacitors connected to the ground. 1.2 I2 C Control STV2000 belongs to the I2C-controlled device family. Each adjustment can be made via the I2C Interface, instead of being controlled by DC voltages on dedicated control pins. The I 2C bus is a serial bus with a clock and a data input. General function and bus protocol are specified in the Philips-bus data sheets. The interface (Data and Clock) is TTL-compatible. Spikes up to 50 ns are filtered by an integrator and the maximum clock speed is limited to 100 kHz. The data line (SDA) can be used bidirectionally. In read mode, the IC sends reply information (1 byte) to the micro-processor. The bus protocol prescribes a full-byte transmission in all cases. The first byte after the start condition is used to transmit the IC address (hexa 8C for write, 8D for read). All bytes are sent MSB bit first and the write data transfer is closed by a stop. 1.3 Write Mode In write mode, the second byte contains the subaddress of the selected function to adjust (or controls to effect) and the third byte the corresponding data byte. More than one data byte can be sent to the IC. If after the third byte no stop or start condition is detected, the circuit automatically increments the momentary subaddress in the subaddress counter (auto-increment mode) by one. Thus it is possible to immediately transmit the following data bytes without sending the IC address or subaddress. This can be useful for reinitializing all the controls very quickly (flash manner). This procedure is ended with a stop condition. There are 19 adjustment capabilities for the circuit: 3 for the horizontal part, 3 for the vertical, 3 for the E/W correction, 2 for the dynamic horizontal phase control, 7 for the preamplifier and 1 for the blanking DC. 14 bits are also dedicated to several controls (ON/OFF). 1.4 Read Mode In the read mode the second byte transmits the reply information. The reply byte contains the horizontal and vertical lock/unlock status, the XRAY activation status. A stop condition always stops all the activities of the bus decoder and switches both the data and clock line (SDA and SCL) to high impedance. See I2C subaddress and control tables. 1.5 Sync Processor The internal sync processor allows the device to receive separate horizontal & vertical TTL-compatible sync signals. 1.6 IC Status The IC informs the MCU about both the 1st horizontal PLL (locked or not) and the XRAY protection (activated or not). The XRAY internal latch is reset either directly via the I2C interface or by decreasing the VCC supply. 1.7 Sync Inputs Both HIN and VIN inputs are TTL compatible triggers with hysterisis to avoid erratic detection. Both inputs include a pull-up resistor connected to VDD. Synchro pulses must be positive.
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STV2000
OPERATING DESCRIPTION (continued)
1.8 Sync Processor Output The sync processor indicates whether 1st PLL is locked to an incoming horizontal sync or not. This is indicated on the D8 bit of the status register . PLL1 level is low when locked. 2. HORIZONTAL PART 2.1 Internal Input Conditions A digital signal (horizontal sync pulse) is sent by the sync processor to the horizontal input. It must be positive (see Figure 4). Synchronization occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7 s. Vertical synchro extraction is not allowed. Figure 4. frequencies. It is followed by a "charge pump", composed of two current sources: sunk and sourced (typically I =1 mA when locked and I = 140 A when unlocked). This difference between lock/unlock allows smooth catching of the horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system when PLL1 is locked, preventing the horizontal frequency from changing too quickly. The dynamic behaviour of PLL1 is fixed by an external filter which integrates the current of the charge pump. A "CRC" filter is generally used (see Figure 5). Figure 5.
Z T
PLL1F 40
1.8k 2.2 PLL1 The PLL1 consists of a phase comparator, an external filter and a voltage-controlled oscillator (VCO). The phase comparator is a "phase frequency" type designed in CMOS technology. This kind of phase detector avoids locking on wrong Figure 6. Block Diagram
Lock/Unlock Status
10nF
4.7F
PLL1F 40
R0 42
C0 41 FC1 43
LOCKDET High
H/HVIN 44
COMP1 Low
CHARGE PUMP 39 Filter
VCO OSC I 2C HPOS Adj.
PHASE ADJUST
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STV2000
OPERATING DESCRIPTION (continued)
Figure 7. Details of VCO
I0 I0 PLL1F 40 (Loop Filter) 42 (1.4V1.6V 0 0.875TH TH 6.4V
2
6.4V
RS FLIP FLOP
1.6V
The VCO uses an external RC network. It delivers a linear sawtooth resulting from the capacitor charge and discharge . The current is proportional to the one in the resistor. Typical thresholds for the sawtooth are 1.6 V and 6.4 V. The VCO control voltage varies between 3.0 V and 3.8 V (see Figure 7). This VCO frequency range is very small. The small effective frequency is due to clamp intervention on the lowest filter value. The PLL1F filter voltage is set by a 4-bit DAC with a voltage range of 3.0 to 3.8 V. The sync frequency must always be higher than the free running frequency. For example, when using a 60 kHz synchro range, the suggested free running frequency is 56 kHz. Figure 8. PLL1 Timing Diagram
H O SC Sawtooth 7/8 TH
1/8 TH
PLL1 ensures the coincidence between the leading edge of the sync signal and a phase reference resulting from the comparison of: - the VCO sawtooth - an internal DC voltage I2C adjustable within the range of 2.9V to 4.2V (corresponding to 10%) (see Figure 8). A Lock/Unlock identification block, also included, detects in real time whether PLL1 is locked on the incoming horizontal sync signal or not. The lock/unlock information is available through the I2C read. The FC1 Pin (Pin 43) is used for decoupling the internal 6.4 V reference by a capacitor.
6.4V 3.4V (Reference for H Position) Vb (2.8VPhase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.9 V and 4.2 V. The PLL1 ensures the exact coincidence between the signal phase REF and HSYNC. A 10% TH phase adjustment is possible around the 3.5V point.
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OPERATING DESCRIPTION (continued)
2.3 PLL2 PLL2 ensures a constant position of the shaped flyback signal in comparison with the sawtooth of the VCO, taking into account the saturation time Ts (see Figure 9). Figure 9. PLL2 Timing Diagram H Osc Sawtooth 7/8TH 1/8TH 6.4V 4.0V 1.6V duction period of the horizontal scanning transistor. The maximum storage time (Ts Max.) is : 0.44TH- TFLY/2). Typically, TFLY/TH corresponds to around 20 % which means that Ts max represents approxim tively 34 % of TH. 2.4 Output Section The H-drive signal is sent to the output through a shaping stage which also controls the fixed Hdrive duty cycle (see Figure 9). In order to secure the scanning power part operation, the output is inhibited in the following cases : -when VCC is too low, -when the ABL protection is activated, -during the Horizontal flyback, -when the HDrive I2C bit control is off. The output stage consists of a NPN bipolar transistor. Only the collector is accessible (see Figure 11). Figure 11.
Flyback Internally Shaped Flyback H Drive Ts Duty Cycle The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output current: 0.5 mA). The flyback input consists of an NPN transistor. This input must be current driven. The maximum recommended input current is 5 mA (see Figure 10). Figure 10. Flyback Input Electrical Diagram 400
HFLY 36 20k Q1
V CC
34 Hout
GND 0V
The duty cycle is fixed at 48%. For a safe start-up operation, the initial duty cycle (after power-on reset) is 85% in order to avoid having too long a con-
This output stage is intended for "reverse" base control, where setting the output NPN in off-state will control the power scanning transistor in offstate. The maximum output current is 15 mA, and the corresponding voltage drop of the output VCEsat is 0.4 V Max. Obviously, the power scanning transistor cannot be directly driven by the integrated circuit. An interface either bipolar or MOS type has to be added between the circuit and the power transistor.
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OPERATING DESCRIPTION (continued)
2.5 X-RAY Protection X-Ray protection is activated when the ABL input (1 V on Pin 20) is at a low level. It inhibits both H-Drive, and Vout while Video goes into off-mode. This activation is internally delayed by 2 lines to avoid erratic detection (short parasitics). This protection is latched; it may be reset either by switching VCC off or by I2C (see Figure 12). Figure 12. Safety Functions Block Diagram
VCC Checking +1V VCC VSCinh XRAY Protection
I2C Drive on/off HORIZONTAL OUTPUT INHIBITION I2C Ramp on/off VERTICAL OUTPUT INHIBITION
+
ABL 20 VCC off or I C Reset
2
S R
Q
Horizontal Flyback 0.7V Video-off
3. VERTICAL PART 3.1 Function When the synchronization pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 100Hz. The typical free running frequency can be calculated according to: 1 fo(Hz) = 1.5 . 10-5 . COSC A positive TTL level pulse applied on Pin 1(Vin) is used to synchronize the ramp in the range [fmin, fmax] (see Figure 13). This frequency range depends on the external capacitor connected on Pin 5. A 150nF ( 5%) capacitor is recommended for 50 Hz to 165 Hz applications. The typical maximum and minimum frequency, at 25 oC and without any correction (S correction), can be calculated as follows: f(Max.) = 3.5 x fo and f(Min.) = 0.33 x fo When an S correction is applied, these values are slightly modified. With a synchronization pulse, the internal oscillator is synchonized immediately but its amplitude changes. An internal correction then adjusts it in less than half a second. The ramp top value (Pin 5) is sampled on the AGC capacitor (Pin 3) at each clock pulse. A transconductance amplifier modifies the charge current of the capacitor so as to make the amplitude constant again. We recommend using an AGC capacitor with a low leakage current. A value lower than 100nA is mandatory. A good level of stability for the internal closed loop is obtained by a 470nF 5% capacitor value on Pin 3 (VAGC). VRB (Pin 8) is used for decoupling the internal 2V reference voltage by a capacitor.
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OPERATING DESCRIPTION (continued)
3.2 I2C Control Adjustments S correction shapes can then be added to this ramp. This frequency-independent S correction is generated internally. Its amplitudes is adjustable via the I2C. S correction can be inhibited by applying the selected bits. Finally, the amplitude of the S corrected ramp is adjustable via the vertical ramp amplitude control register.The adjusted ramp is available on Pin 6 (VOUT) to drive an external power stage. Figure 13. AGC Loop Block Diagram
CHARGECURRENT TRANSCONDUCTANCE AMPLIFIER REF 5 DISCH.
VSYNCIN
The gain of this stage can be adjusted ( 25%) depending on its register value. The mean value of this ramp is driven by its own I2C register (vertical position) with : VPOS = 7/16 x VREF-V = 300 mV. Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from VREF-V, the bias voltage sent to the noninverting input of the booster should also derive from VREF-V to optimize the accuracy (see Figure 13).
OSC CAP
3 SAMPLING SAMPLING CAPACITANCE
1
SYNCHRO
OSCILLATOR S CORRECTION VS AMP SUB07/7bits Vlow 7 BREATH
Sawth Disch.
6 VOUT VERT AMP SUB08/7bits VPOSITION SUB09/7bits
3.3 Basic Equations As a first approximation, the amplitude of the ramp on Pin 6 (VOUT) is calculated as follows:
V OUT - VPOS = (VOSC - VDCMID) x (1 + 0.25 (VAMP))
where : VDCMID = 7/16 x VREF (middle value of the ramp on Pin 5, typically 3.6V) VOSC = V5 (ramp with fixed amplitude) VAMP = -1 as minimum vertical amplitude register
value and +1 as maximum value. VPOS is calculated according to: VPOS = VDCMID + (0.4x VP ) where VP = -1 and +1 as respectively minimum and maximum vertical position register value. The current available on Pin 5 is: 3 IOSC = x VREF x COSC x f 8 where COSC = capacitor connected on Pin 5 f = synchronization frequency.
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OPERATING DESCRIPTION (continued)
3.4 Geometric Corrections The principle is represented in Figure 14. Starting from the vertical ramp, a parabola-shaped current is generated for E/W correction (also known as Pin Cushion correction), dynamic horizontal phase control correction. The parabola generator consists of an analog multiplier, the output current of which is equal to : I = k x (VOUT - VDCMID) 2 where VOUT is the vertical output ramp (typically between 2 and 5 V) and VDCMID is 3.6 V (for VREF-V = 8.2V). The VOUT sawtooth is typically centered on 3.6 V. By changing the vertical position, the sawtooth shifts by 0.4 V. The "geometry tracking" feature ensures a correct screen geometry for any end user adjustment. It generates non-symmetric parabola dependent on the vertical position. Due to the large output stage voltage range (E/W Pin Cushion, Keystone), the combination of the tracking function, maximum vertical amplitude, maximum or minimum vertical position and maxiFigure 14. Geometric Corrections Principle mum gain on the DAC control may lead to output stage saturation. This must be avoided by limiting the output voltage with appropriate I2C register values. For the E/W part and the dynamic horizontal phase control part, a sawtooth-shaped differential current in the following form is generated: I' = k' . (VOUT - VDCMID). Then I and I' are added and converted into voltage for the E/W part. Each of the two E/W components or the two dynamic horizontal phase control components may be inhibited by their own I2C select bit. Internal EW correction voltage is not available directly on the output pin. The EW correction is obtained with the feedback voltage (Pin 27: EWBin) which generates a modulating current in the diode (Pin 28). In addition, the horizontal width is I2Ccontrolled. The dynamic horizontal phase control drives the H-position internally, moving the HFLY position on the horizontal sawtooth in the range of 2.8 %TH both for side pin balance and parallelogram.
3.5 E/W EWOUT = EWDC + K1 (VOUT - VDCMID) +K2 (VOUT - VDCMID)2 K1 is adjustable via the keystone I2C register. K2 is adjustable via the E/W amplitude I2C register.
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OPERATING DESCRIPTION (continued)
3.6 Dynamic Horizontal Phase Control IOUT= K4 (VOUT - VDCMID) + K5 (VOUT - VDCMID)2 K4 is adjustable via the parallelogram I2C register. K5 is adjustable via the side pin balance I2C register. 3.7 Horizontal Breathing Horizontal breathing compensation is performed through the EW stage with the Voltage-Current Converter. This DC-controlled input provides the required horizontal width corrections to offset width changes arising from EHT variations. 3.8 Vertical Breathing Vertical breathing compensation is performed through the gain modulation of the vertical ramp. This DC-controlled input provides the vertical height corrections required to offset height changes arising from EHT variations.
B PRE-AMPLIFIER PART
1. GENERAL CONSIDERATIONS 1.1 Input Stage The R, G and B signals must be supplied to the three inputs through coupling capacitors (100nF). The maximum input peak-to-peak video amplitude is 1 V. Figure 15. . The input stage includes a clamping function. This clamp uses the input serial capacitor as "memory capacitor" and is gated by an internally generated "Back-Porch-Clamping-Pulse (BPCP)". The BPCP is synchronized on the second edge of the horizontal pulse HIN inputs on Pin 44.
HSYNC
BPCP
Internal pulse width is fixed at 1s In both cases, BPCP width is fixed. 1.2 Contrast Adjustment (7 bits) The contrast adjustment is made by simultaneously controlling the gain of three internal variable gain amplifiers through the I2C bus interface. The contrast adjustment allows covering a range higher than 40 dB. This adjustment is refreshed during the vertical retrace time. 1.3 ABL Control The STV2000 has an ABL input (automatic beam limitation) to attenuate RGB video signals according to beam intensity. The operating range is typically 2.5 V, from 5.3 V to 2.0 V. A typical 12 dB Max. attenuation is applied to the signal whatever the current gain. Refer to Figure 16 for ABL input attenuation range. In the case of software control, the ABL input must be pulled to AVCC through a resistor to limit power consumption. ABL input voltage must not exceed VAVCC . Input resistor is 10k.
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STV2000
OPERATING DESCRIPTION (continued)
Figure 16.
2 0 -2 -4 -6 -8 -10 -12 -14 1 2 3 4 5 6 7 VIN(V) 8 9 Attenuation (dB)
large drive adjustment range (48dB) allows different standard or custom color temperatures. The drive adjustment is also used to adjust the output voltages at the optimum amplitude to drive the C.R.T drivers, keeping the whole contrast control for end-users only. The drive adjustment is made after the contrast and brightness so that the white balance remains correct when BRT is adjusted. 1.6 Output Stage The three output stages (see Figure 17) incorporate three functions: * The blanking stage: when the internal generated blanking pulse is high, the three outputs are switched to a voltage which is 400 mV lower than the BLACK level. The black level is the output voltage with minimum brightness when the input signal video amplitude is equal to "0". * The output stage itself: a large bandwidth output amplifier which can deliver up to 5VPP on the three outputs (for 0.7 V video signal on the inputs). * The output CLAMP: the IC also incorporates three internal output clamps (sample and hold system) used for the DC to shift the three output signals. The DC output voltage is fixed at 1.5 V. The overall waveforms of the output signal according to the different adjustments are shown in Figure 18.and Figure 19.
1.4 Brightness Adjustment (6 bits) As with contrast adjustment, brightness is controlled by I2C. The brightness function consists of adding the same DC offset to the three R, G, B signals after contrast amplification. This DC-Offset is present only outside the blanking pulse (see Figure 18). The DC output level is forced to "INFRA-BLACK" level (VDC) during the blanking pulse. 1.5 Drive Adjustment (3 x 8 bits) To adjust the white balance, the device offers the possibility of separately adjusting the overall gain of each complete video channel. Each channel gain is controlled by I2C (8 bits each). The very Figure 17.
10
Vout
CRT Driver
S/H
1.5V Cut-off DAC 8 bits
11 Cut-off
STV2000
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OPERATING DESCRIPTION (continued)
Figure 18. Waveforms VOUT, BRT, CONT HSYNC BPCP BLK Video IN VOUT1, VOUT2, VOUT3 VCONT (4) CONT VBRT (3) VBLACK (2) VDC (1) BRT 0.4V fixed
Note : 1. VDC = 1.5V 2. VBLACK = VDC + 0.4V 3. VBRT = VBLACK + BRT (with BRT = 0 to 2.5V) 4. VCONT = VBRT + CONT with CONT = k x video (CONT = 5VPP max. for VIN = 0.7V PP)
Figure 19. Waveforms (DRIVE adjustment)
HSYNC BPCP BLK Video IN
VOUT1 , V OUT2 , VOUT3 VCONT
VBRT
two examples of drive adjustment (1) Note : 1. Drive adjustment modifies the following voltages : VCONT, VBRT. . Drive adjustment does not modify the following voltages : VDC and VBLACK.
VBLACK VDC
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STV2000
OPERATING DESCRIPTION (continued)
1.7 Cutoff DAC Output Three Cutoff DACs (8 bits) with output buffers are incorporated to drive the external cutoff circuit. Output voltage range is from 0.5 V to 4.5 V. 1.8 Blanking Generator A vertical blanking pulse is generated (see Figure 20). The output level is a positive going pulse of 8V. The vertical blanking is started by the vertical sync pulse and the duration is determined by counting 22 horizontal periods. If there is no vertical sync pulse the vertical blanking start coincides with the beginning of the vertical capacitor discharge time. The blanking output generates a superimposed variable DC voltage. The 6-bit adjustment range is 1 V to 4.5 V. This is used to allow brightness control through G1. Additionally, this pin is used for spot killer suppression. The 0.8 V of Vcc threshold will trigger the output into a high level state resulting from the Vcc decay.
Figure 20. VBDC (Pin 24) Output Voltage Waveform
22 H lines DC level controlled by 6-bit DAC 8V 4.5 V 1.0 V
1.9 DAC Output This is a 7-bit DAC with 1 output pin. An output buffer is used to enhance load capability with an Imax(source) of 2 mA. Table 1: Logic Table
Hout no yes no yes no yes on/off yes yes yes yes Vout no yes no yes no yes yes on/off yes yes yes Video-off video-off video-off video-off video-off video-off video-off on/off on/off on/off video-on (2) video-on (2) Low Power NA (1) NA(1) yes no no no no no no NA (1) no Conditio ns Vcc at 0 to 6.9 V (PD2 mode) Vcc at 6.9 V to 8.5 V (PD1 mode) I2C DPMS bit=1, (default=0) Hlock/unlock detection = unlock Video ABL input pin < 1 V 5 V POR or I2C POR=1, (default=0) I2C Hout on/off, (default=1=on) I2C Vout on/off, (default=1=on) I2C Video on/off, (default=0=video-off) Vcc at >8.5 V Vcc at >8.5 V, I2C video=1=on
Note 1 NA= Not applicable. Note 2 I2C video=on will be reset by I2CDPMS/Low Vcc.
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OPERATING DESCRIPTION (continued) C STAND-BY MODE AND PROTECTIONS
1. GENERAL CONSIDERATIONS 1.1 POR (Power On Reset) - Subadress 11- D8 POR is activated on 5 V with default values for each adjustment and in addition video off (see 1.3). It can be activated via the I2C command. 1.2 Supply Voltage Threshold. Two built-in thresholds (see figure 21) are used to enter the following modes: * PDI mode: - Activated for Vcc < 8.5V - Video off (see 1.13) * PD2 mode: - Activated for Vcc < 6.9V - Video off (see 1.13) - HOUT and VOUT disabled 1.3 Video Off (I2C control) - Subadress 00 - D8 Activates blanking of the 3 video output stages. During this time the outputs are switched to ground level, regardless of the presence of Hsync or Hflyback. Activation time is inferior to 1s. This also activates the blanking output generating a positive going signal at pin 24 as long as "video off" is activated. 1.4 Vertical Output Off This command will switch off output VAMP. The vertical output swing is reduced to 0V. During power saver mode, the total vertical section is disabled. 1.5 Power Saver On - Subadress 11 - D7 This I2C command activates the PD1 and PD2 mode regardless of the scanning Vcc value. Internal scanning and pre-amp voltage are off. During "power saver" mode, the device power consumption will be reduced to below 20mA for all supply pins. Vdd, I2C interface and DAC data are not affected by this command. 1.6 X-Ray, Set Operation - Subadress 09 - D8 When ABL voltage is below 1 V threshold, Xray latch will be activated. This I2C command will reset the Xray latch. Activation time below 100ms.
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STV2000
INTERNAL SCHEMATICS
Figure 21. Figure 24.
VDD 200k
SAV CC
1+ 44
200
Vgnd
4
Figure 22.
SAVCC
Figure 25.
SAVCC
VCAP 5
Vref 2 22k
Figure 23.
Figure 26.
SAV CC
SAVCC
VAGCCAP
3
VOUT 6
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STV2000
INTERNAL SCHEMATICS (continued)
Figure 27. Figure 30.
SAVCC
Pins 19 21 23 IN
VAVCC
V BREATH
7
Agnd
Agnd
Figure 28.
Figure 31.
VAVCC
VAVCC 9 12V BIPSWITCH
Internal 5V
20
AGND
10k
Agnd
10k
Figure 29.
Figure 32.
PVCC VAV CC
VAVCC
Pins 10, 13, 16
Agnd Pgnd
Pin 11 14 17 Agnd
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STV2000
INTERNAL SCHEMATICS (continued)
Figure 33. Figure 36.
VAVCC
VAVCC
Agnd 12
DAC 22
50
AGND
Figure 34.
Figure 37.
VAVCC
VBDC 24
Pgnd 15
Figure 35.
Figure 38.
SAVCC
VAVCC
60K HBreath 26 Vref
PVCC 18
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INTERNAL SCHEMATICS (continued)
Figure 39.
SAVCC Vref
VDD 5V
Figure 42.
EWFB 27
10K SDA 30
Figure 40.
Figure 43.
SAV CC Vref
5V
VDD
1.5k
10k
EWout 28
SCL 31
10k
Figure 41.
Figure 44.
V DD 29 5V BIPSWITCH
SAVCC 32 12V BIPSWITCH
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STV2000
INTERNAL SCHEMATICS (continued)
Figure 45. Figure 48.
Href 35 SAVCC
Lgnd 33
HFLY 36
Figure 46.
SAVCC
Figure 49.
HOUT 34
Hgnd 37
Figure 47.
SAV cc
Figure 50.
SAV CC
Href
PLL2C 38
Href 35 22k
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STV2000
INTERNAL SCHEMATICS (continued)
Figure 51. Figure 54.
Href Href 35
SAVCC
Href
SAVCC
42
Filter 39
Figure 52.
Figure 55.
SAVCC Href
SAVCC 1K _ 3 FC1 43 4K _ 3
PLL1F 40
Figure 53.
SAVCC Href 35
Figure 56.
SAVCC Vref R1
41
VRB
8 R2
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6490
C32 4u7
47u C37
C33 10n C34 Vcc 6 QA N1B 11 QB 10 NQB 9 R15 10K +5V C7 33p R13 1K Vcc C6 10u Hout R12 560 D1 1N4148 C14 100u C16 100u 7 NQA Vcc 8 GND 5 N1A 1B 12
C35 22n
100n C36
C30 100n
Vcc R0 FC1 C0 HFLY PLL1F FILTER PLL2C HGND HREF
C28 100n
R32 1K SCL 31 SDA 30 VDD 29 C13 100n
C29 47u
1u 44 43 42 41 40 39 38 37 36 35 34 HIN HOUT 1 VIN LGND 33 C15 100n 2 VREF SAVCC32
R33 10K
C27 470n
3 VAGCCAP
4 VGND
C26 150n
VOUT R31 12K
5 VCAP
R35
C31 820p R36 1K8
CUTOFF2
OUT3
CUTOFF3
PVCC
IN1
ABLIN
PGND
IN2
C23 100n
C24 100u
C20 100n
C19 100n
C17 100n
R4 1K
R6 10K
R2 1K
OUT3 L1 10uH R25 75 IN1 IN2 R24 75 Vcc
CUTOFF3
R23 75 IN3
R5 10K
R3 10K
R1 10K
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C8 33p HFLY R14 10K Vcc R37 47K Vcc HREF C11 C10 MC14528 C12 10u 100n VCC16 1 TA1 47p R38 47K C9 2 TA2 TB1 15 47p Delay TB2 14 Vcc 3 CDA Width R16 10K CDB13 4 1A
STV2000
HIN
VIN
R31 10K EWFBIN27 HBRTH 26 NC 25 VBDC 24 R18 25K Vcc R17 1K EW
6 VOUT
STV2000
EWOUT 28
7 VBRTHIN
Figure 57. STV2000 Demonstration Board Schematics
C25 100n
C39 1u
8 VRB
Vcc
9 VAVCC
L3 10uH
10OUT1
11CUTOFF1 IN3 23 DAC AGNDOUT2 12 13 14 15 16 17 18 19 20 21 22 C3 200p DAC Vcc
+5V R8 4K7 BD677 R9 4K7 5V R10 100 SDA R11 100 SCL C4 22p C5 22p GND
OUT1 R19 2K R20 47
CUTOFF1 C21 100u C22 100n R22 47 R21 47
OUT2
CUTOFF2
STV2000
PACKAGE MECHANICAL DATA
44-Pin Thin Quad Flat Package
D D1 D3 33 23 22
0.10m m .004
A A2 A1
34
b
E3 E1 E
44
12
PIN 1 IDENTIFICATION 1 e
11
c
L1
L K
Dimensions A A1 A2 b c D D1 D3 E E1 E3 e K L L1 N
Millimeters Min. 0.05 1.35 0.30 0.09 12.00 10.00 8.00 12.00 10.00 8.00 0.80 0 0.45 3.5 0.60 1.00 Number of Pins 44 7 0.75 0.018 1.40 0.37 Typ. Max. 1.60 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.004 Min.
Inches Typ. Max. 0.063 0.006 0.055 0.015 0.472 0.394 0.315 0.472 0.394 0.315 0.031 0.024 0.039 0.030 0.057 0.018 0.008
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STV2000
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change witho ut notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2000 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China -Finland - France - Germany -Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www .st.com
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